High speed viterbi decoder for W-LAN and broadband applications

Conference Proceedings - 2nd Annual IEEE Northeast Workshop on Circuits and Systems, NEWCAS 2004

Volumn , Issue , 2004, Pages 25-28

  Abdul Shakoor, A R ^a   Szwarc, V ^a   Kwasniewski, T A ^b  

^a Radio Science Branch   (Canada)

^b CARLETON UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BROADBAND NETWORKS; COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; CONSTRAINT THEORY; DECODING; FIELD PROGRAMMABLE GATE ARRAYS; LOCAL AREA NETWORKS; MAXIMUM LIKELIHOOD ESTIMATION; STANDARDS; WIRELESS TELECOMMUNICATION SYSTEMS;

ADD COMPARE SELECT (ACS); TRACK-BACK LENGTHS (TBL); VITERBI ALGORITHMS; VITERBI DECODER;

INTEGRATED CIRCUITS;

EID: 14844323020     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. IEEE 802.11a Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications, July 1999.
2. IEEE P802.16.3c-01/33r2, Version 0.46, PHY Draft Standard for Local and Metropolitan Area Networks-Part 16, pp. 36-38, March 2001.
3. P. J. Black and T. H. Meng, "A 140 MBPS, 32-State, Radix-4 Viterbi Decoder," IEEE JSSC, vol. 27, no. 12, pp. 1877-1885, December 1992.
4. G. Fettweis and H. Meyr, "High-Speed Parallel Viterbi Decoding: Algorithm and VLSI Architecture," IEEE Communications Magazine, vol. 29, no. 5, pp. 46-55, May 1991.
5. S. J. Lee, M. Goel and N. R. Shanbag "High-Speed FEC FPGA Design for MIMO-OFDM based W-LAN Modem," International Signal Processing Conference, Dallas, April 2003.
6. R. J. McEliece and I. M. Onyszchuk, "Truncation Effects in Viterbi Decoding," MILCOM, vol.1, pp. 541-545, 1989.
7. B. Shim and J. C. Suh, "Pipelined VLSI Architecture of The Viterbi Decoder for IMT-2000," GLOBECOM, vol.1a, pp.158-162, 1999.
8. Altera, "Implementing an IEEE 802.16 compliant FEC decoder," www.altera.com/literature/wp/wp_ieee80216.pdf.
9. H. L. Lou, "Implementing the Viterbi Algorithm," IEEE Signal Processing Magazine, pp. 42-52, September 1995.
10. B. Nikolic, "Algorithmic and Circuit Techniques in Digital Viterbi Decoder For Magnetic Recording Channel," Ph.D. Dissertation, Dept. of Electrical and Computer Engineering, University of California at Davis, 1999.