Coaxial polymer pillars: Ultra-low inductance compliant wafer-level electrical input/output interconnects for power distribution

Proceedings - IEEE International SOC Conference

Volumn , Issue , 2004, Pages 78-81

  Shakeri, Kaveh ^a   Bakir, Muhannad ^a   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Package; Power distribution; Simultaneous switching noise and ground bounce; VLSI

Indexed keywords

ELECTRIC POTENTIAL; ELECTRIC POWER DISTRIBUTION; ELECTROOPTICAL DEVICES; INDUCTANCE; POLYMERS; SEMICONDUCTING FILMS; SILICA; SWITCHING; VLSI CIRCUITS;

CHIP-TO-CHIP INTERCONNECTIONS; PACKAGE; SIMULATANEOUS SWITCHING NOISE (SSN); SIMULTANEOUS SWITCHING NOISE AND GROUND BOUNCE;

ELECTRIC POWER SYSTEM INTERCONNECTION;

EID: 14844314441     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. M. Bakir, T. Gaylord, K. Martin, J. Meindl, "Sea of polymer pillars: compliant wafer-level electrical-optical chip I/O interconnections," IEEE Photonics Technol. Lett., vol. 15, no. 11, 2003, pp. 1567-1569.
2. M. Bakir, A. Mule, T. Gaylord, P. Kohl, K. Martin, and J. Meindl, "Sea of dual-mode polymer pillar I/O interconnections for gigascale integration," in Proc. IEEE Int. Solid-State Circuits Conf., 2003, pp. 372-373.
3. David K. Cheng, Field and Wave Electromagnetics, Addison Wesley, Reading, MA, 1989.
4. H. B. Bakoglu, Circuits, Interconnections and packaging for VLSI, Addison-Wesley, 1990.