Layout optimization on low-voltage-triggered PNP devices for ESD protection in mixed-voltage I/O interfaces

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Volumn , Issue , 2004, Pages 213-216

  Chang, Wei Jen ^a   Ker, Ming Dou ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC BREAKDOWN; ELECTRIC DISCHARGES; ELECTROSTATICS; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; OPTIMIZATION; SIGNAL PROCESSING;

ELECTROSTATIC DISCHARGES (ESD); HUMAN-BODY-MODELS (HBM); LOW-VOLTAGE-TRIGGERED PNP (LVTPNP); MIXED-VOLTAGE I/O INTERFACES;

ELECTRIC POTENTIAL;

EID: 14844310333     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. S. H. Voldman, "ESD protection in a mixed voltage interface and multi-rail disconnected power grid environment in 0.5- and 0.25-μm channel length CMOS technologies," in Proc. of EOS/ESD Symp., 1994, pp. 125-134.
2. S. Dabral and T. J. Maloney, Basic ESD and I/O Design, John Wiley & Sons, Inc., New York, 1998.
3. M.-D. Ker, W.-J. Chang, and W.-Y. Lo, "Low-voltage-triggered PNP devices for ESD protection design in mixed-voltage I/O interface with over-VDD and under-VSS signal levels" in Proc. of IEEE Int. Symp. on Quality Electronic Design, 2004, pp. 433-438.
4. Standard Test Method for Component-Level Electrostatic Discharge Sensitivity - Human Body model (HBM), ESD Association, STM 5.1, 2001.
5. G. Notermans, A. Heringa, M. Van Dort, S. Jansen, and F. Kuper, "The effect of silicide on ESD performance," in Proc. of IEEE Int. Reliability Physics Symp., 1999, pp. 154-158.