Low-voltage-triggered PNP devices for ESD protection design in mixed-voltage I/O interface with over-VDD and under-VSS signal levels

Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004

Volumn , Issue , 2004, Pages 433-438

  Ker, Ming Dou ^a   Chang, Wei Jen ^a   Lo, Wen Yu ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b Silicon Integrated Systems group   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; ELECTRIC DISCHARGES; ELECTRIC POTENTIAL; ELECTRIC POWER SYSTEMS; LEAKAGE CURRENTS; OPTIMIZATION;

CARRIER DEGRADATION; HUMAN-BODY MODEL (HBM); I/O INTERFACES;

MOSFET DEVICES;

EID: 2942657465     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/isqed.2004.1283712     Document Type: Conference Paper

References (3)

1. S. H. Voldman, "ESD protection in a mixed voltage interface and multi-rail disconnected power grid environment in 0.5- and 0.25-μm channel length CMOS technologies," in Proc. of EOS/ESD Symp., 1994, pp. 125-134.
2. S. Dabral and T. J. Maloney, Basic ESD and I/O Design, John Wiley & Sons, Inc., New York, 1998.
3. Standard Test Method for Component-Level Electrostatic Discharge Sensitivity - Human Body model (HBM), ESD Association, STM 5.1, 2001.