Design Trade-offs for a 10 Bit, 80 MHz Current Steering Digital-to-Analog Converter

Conference Proceedings - 2nd Annual IEEE Northeast Workshop on Circuits and Systems, NEWCAS 2004

Volumn , Issue , 2004, Pages 249-252

  Baschirotto, A ^a   Ghittori, N ^b   Malcovati, P ^b   Vigna, A ^b  

^a UNIVERSITY OF SALENTO   (Italy)

^b UNIVERSITY OF PAVIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL COMMUNICATION SYSTEMS; ERROR ANALYSIS; LOCAL AREA NETWORKS; MONTE CARLO METHODS; TRANSMITTERS; WIRELESS TELECOMMUNICATION SYSTEMS;

DIFFERENTIAL NON LINEARITY (DNL); INTEGRAL NON LINEARITY (INL); RADIO FREQUENCY (RF); RECONSTRUCTION FILTERS; WIRELESS LOCAL AREA NETWORKS (WLAN);

DIGITAL TO ANALOG CONVERSION;

EID: 14844290305     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. IEEE Standard 802.11a-1999: Wireless LAN MAC and PHY Specifications - High Speed Physical Layer in the 5 GHz Band, New York. IEEE, 2000.
2. Y. Cong, R.L. Geiger, "Formulation of INL and DNL yield estimation in current steering D/A converters", ISCAS 2002, vol. 3, pp 149-152, May 2002.
3. M.J.M. Pelgrom, A.C.J. Duinmaijer and A.P.G. Welbers, "Matching properties of MOS transistor", IEEE J. Solid-State Circuits, vol. 24, pp. 1433-1439, Oct. 1989.
4. J.J. Wikner, N.Tan, "Modeling of CMOS Digilal-to-Analog Converters for Telecommunication", IEEE Transactions on Circuits and Systems, vol. 46, pp. 489-499, May 1999.