A new architecture for area and power efficient, high conversion rate successive approximation ADCs

Conference Proceedings - 2nd Annual IEEE Northeast Workshop on Circuits and Systems, NEWCAS 2004

Volumn , Issue , 2004, Pages 253-256

  Dabbagh Sadeghipour, Khosrov ^a   Hadidi, Khayrollah ^a   Khoei, Abdollah ^a  

^a URMIA UNIVERSITY   (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; ELECTRIC POTENTIAL; INTERPOLATION;

BIT EXTRACTION; DOUBLE POLY, TRIPLE METAL (DPTM) CMOS TECHNOLOGY; SUCCESSIVE APPROXIMATION REGISTER (SAR);

ANALOG TO DIGITAL CONVERSION;

EID: 14844283824     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. T.B. Cho, et al, "Design consideration for high-speed low-power low-voltage CMOS analog-to-digital converters", IEEE Symp. Low-Power Electronics, pp.461-464, 1994.
2. A.R. Nabavi, Kh. Dabbagh, "A 10-bit, 20Ms/S, 22mW folding and interpolating CMOS ADC", IEEE Int. Conf. Microelectronics, pp.43-46, 2000.
3. J. Yuan, C. Svensson, "A 10-bit 5-MS/s Successive Approximation ADC Cell Used in a 70- MS/ s ADC Array in 1.2-μm CMOS", IEEE J. Solid-State Circuits, vol.29, pp.866-872, August 1994.
4. B. Fotouhi, D.A. Hodges, "High- Resolution A/ D Conversion in MOS/LSI", IEEE J. Solid-State Circuits, vol.sc-14, pp.920-926, December 1979.
5. K. Bacrania, "A 12-bit Successive-Approximation-Type ADC with Digital Error Correction", IEEE J. Solid-State Circuits, vol.sc-21, pp.1016-1025, December 1986.
6. K. Hadidi, V.S. Tso, G.C. Temes, "An 8-bit 1.3MHz successive approximation A/D converter", IEEE J. Solid-State Circuits, vol.25, pp.880-885, June 1990.
7. J.L. McCreary, P.R. Gray, "All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques", IEEE J. Solid-State Circuits, vol.sc-10, pp.371-379, December 1975.
8. H. Ghoddami, "A 10-bit 50-Ms/S parallel successive-approximation A/D," M.S. thesis, Urmia University, Iran, 1998.
9. W.C. Black, D.A. Hodges, "Time Interleaved Converter Arrays" IEEE J. Solid-State Circuits, vol.sc-15, pp.1022-1029, December 1980.
10. A. Petraglia, S.K. Mitra, "Analysis of mismatch effect among A/D converters in a time-interleaved waveform digitizer", IEEE Trans. Instrumentation and Measurement, vol.40, October 1991.
11. A.M. Abo, P.R. Gray, "A 1.5V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter", IEEE Journal of Solid-State Circuits, vol.34, pp.599-606, May 1999.
12. T.B. Cho, P.R. Gray, "A 10-b, 20-Msample/s, 35-mW pipeline A/D converter", IEEE Journal of Solid-State Circuits, vol.30, pp. 166-172, March 1995.