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Volumn , Issue , 2004, Pages 236-239

1.0 GBPS LVDS transceiver design for LCD panels

Author keywords

CMFB; High speed D latch; LVDS signaling; Positive feedback; Regulator

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; FEEDBACK; INPUT OUTPUT PROGRAMS; INTEGRATED CIRCUIT LAYOUT; PRINTED CIRCUIT BOARDS; TRANSCEIVERS; VOLTAGE CONTROL;

EID: 14544271482     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (10)

References (8)
  • 2
    • 0035309966 scopus 로고    scopus 로고
    • LVDS I/O interface for Gb/s-per-pin operation in 0.35-μm CMOS
    • Apr.
    • A. Boni, A. Pierazzi, and D. Vecchi, "LVDS I/O interface for Gb/s-per-pin operation in 0.35-μm CMOS," IEEE J. of Solid-State Circuits, vol. 36, no. 4, pp. 706-711, Apr. 2001.
    • (2001) IEEE J. of Solid-state Circuits , vol.36 , Issue.4 , pp. 706-711
    • Boni, A.1    Pierazzi, A.2    Vecchi, D.3
  • 4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.