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Volumn E87-A, Issue 2, 2004, Pages 357-363

Differential Voltage (ΔV) Comparator with Variable Channel-Size MOSFET

Author keywords

Channel size; Comparator; Variable; VS MOS; VT INV

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER SIMULATION; ELECTRIC FIELD EFFECTS; ELECTRIC INVERTERS; ELECTRIC POTENTIAL; LSI CIRCUITS; MOSFET DEVICES; TRANSISTORS;

EID: 1442357400     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (6)

References (6)
  • 1
    • 0031075503 scopus 로고    scopus 로고
    • A fully differential comparator using a swilched-capacitor differencing circuit with common-mode rejection
    • Feb.
    • T. Shin, L. Der, S. Lewis, and P. Hurst, "A fully differential comparator using a swilched-capacitor differencing circuit with common-mode rejection," IEEE J. Solid-State Circuits, vol.32, no.2, pp.250-253, Feb. 1997.
    • (1997) IEEE J. Solid-State Circuits , vol.32 , Issue.2 , pp. 250-253
    • Shin, T.1    Der, L.2    Lewis, S.3    Hurst, P.4
  • 2
    • 0033699021 scopus 로고    scopus 로고
    • Low power/low voltage high speed CMOS differential track and latch comparator with rail-to-rail input
    • May
    • C. Fayomi, G. Roberts, and M. Sawan, "Low power/low voltage high speed CMOS differential track and latch comparator with rail-to-rail input," IEEE Int. Symposium on Circuits and Systems (ISCAS2000), pp.653-656, May 2000.
    • (2000) IEEE Int. Symposium on Circuits and Systems (ISCAS2000) , pp. 653-656
    • Fayomi, C.1    Roberts, G.2    Sawan, M.3
  • 3
    • 85027165822 scopus 로고    scopus 로고
    • An adjustable ßMOSFET (A-MOS)
    • Nov.
    • Y. Arima and T. Asano, "An adjustable ßMOSFET (A-MOS)," IEEJ System LSI Workshop, pp.271-274, Nov. 2001.
    • (2001) IEEJ System LSI Workshop , pp. 271-274
    • Arima, Y.1    Asano, T.2
  • 4
    • 1442316437 scopus 로고    scopus 로고
    • A logic threshold voltage conversion circuitry with variable channel-size MOSFET
    • Aug.
    • Y. Arima, N. Nakanose, and T. Asano, "A logic threshold voltage conversion circuitry with variable channel-size MOSFET," IEICE Trans. Electron. (Japanese Edition), vol.186-C, no.8, pp.894-901, Aug. 2003.
    • (2003) IEICE Trans. Electron. (Japanese Edition) , vol.186 C , Issue.8 , pp. 894-901
    • Arima, Y.1    Nakanose, N.2    Asano, T.3
  • 5
    • 27944492851 scopus 로고
    • A functional MOS transistor featuring gate-level weighted sum and threshold operations
    • June
    • T. Shibata and T. Ohmi, "A functional MOS transistor featuring gate-level weighted sum and threshold operations," IEEE Trans. Electron Devices, vol.39, no.6, pp.1444-1455, June 1992.
    • (1992) IEEE Trans. Electron Devices , vol.39 , Issue.6 , pp. 1444-1455
    • Shibata, T.1    Ohmi, T.2
  • 6
    • 0036475752 scopus 로고    scopus 로고
    • Analog inverter with neuron-MOS transistor and its application
    • Feb.
    • M. Inaba, K. Tanno, and O. Ishizuka, "Analog inverter with neuron-MOS transistor and its application," IEICE Trans. Fundamentals, vol.E85-A, no.2, pp.360-365, Feb. 2002.
    • (2002) IEICE Trans. Fundamentals , vol.E85-A , Issue.2 , pp. 360-365
    • Inaba, M.1    Tanno, K.2    Ishizuka, O.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.