Image processing algorithms on reconfigurable architecture using HandelC

Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004

Volumn , Issue , 2004, Pages 218-226

  Muthukumar, V ^a   Rao, Daggu Venkateshwar ^a  

^a University of Nevada Las Vegas   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

IMAGE PROCESSING ALGORITHMS; PERIPHERAL DEVICES; PROTOTYPING; RECONFIGURABLE ARCHITECTURES;

ALGORITHMS; C (PROGRAMMING LANGUAGE); COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; FIELD PROGRAMMABLE GATE ARRAYS; IMAGE RECONSTRUCTION; MATHEMATICAL MODELS; VLSI CIRCUITS;

IMAGE PROCESSING;

EID: 13944273757     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2004.1333280     Document Type: Conference Paper

References (15)

1. John C. Ross. "Image Processing Hand book", CRC Press. 1994.
2. Stephen D.Brown, R.J. Francis, J.Rose, Z.G.Vranesic "Filed Programmable Gate Arrays", 1992.
3. Moore,M "A DSP-based real time image processing sytem". In the Proceedings of the 6th International conference on signal processing applications and technology, Boston MA, August 1995.
4. Rolf F. Molz, Paulo M. Engel, Fernando G. Moraes, Lionel Torres, Michel Robert. "Design of a Classification System for Rectangular Shapes Using a Co-Design Environment". In the 13th Symposium on Integrated Circuits and Systems Design, 01/01/2000, pp. 281-286.
5. Richard G.Shoup. "Parameterized Convolution Filtering in a Field Programmable Gate Array Interval". Technical Report, Palo Alto, California. 1993.
6. "3×3 Convolver with Run-Time Reconfigurable Vector Multiplier in Atmel AT6000 FPGAs". AT6000 FPGAs Application Note 1997.
7. V.Gemignani, M. Demi, M Paterni, M Giannoni and A Benassi. "DSP implementation of real time edge detectors". In the Proceedings of speech and image processing pp 1721-1725, 2001.
8. J.Canny. "A computational approach to the edge detection". IEEE Trans Pattern and Machine Intelligent. Vol PAMI-8 1986 pp 679-698.
9. F.G.Lorca, L Kessal and D.Demigny. "Efficent ASIC and FPGA implementation of IIR filters for Real time edge detection". In the International Conference on image processing (ICIP-97) Volume 2. Cct 1997.
10. Fahad Alzahrani, "Tom Chen Real-time high performance Edge detector for computer vision applications". In the Proceedings of ASP-DAC, 1997, pp 671-672.
11. Celoxica Ltd. www.celoxica.com
12. Peter Mc Curry, Fearghal Morgan, Liam Kilmartin. Xilinx FPGA implementation of a pixel processor for object detection applications. Proc. Irish Signals and Systems Conference 2000.
13. Xilinx VertexTM-E Field Prgrammable Gate Arrays (V2.4) "July 17, 2002 Production Product specification".
14. Venkateshwar Rao Daggu. "Design and Implementation of an Efficient Reconfigurable Architecture for Image Processing Algorithms using Handel-C". Masters Thesis, UNLV, 2003.
15. Man Ng: High Level Design For High Speed FPGA Devices.Master's Thesis, Dept of computing. Imperial College. June 13. 2002.