Experimental validation of crosstalk simulations for on-chip interconnects using S-parameters

IEEE Transactions on Advanced Packaging

Volumn 28, Issue 1, 2005, Pages 57-62

  Kobrinsky, Mauro J ^a   Chakravarty, Sourav ^a   Jiao, Dan ^a   Harmes, Michael C ^a   List, Scott ^b   Mazumder, Mohiuddin ^a  

^a INTEL CORPORATION   (United States)

^b IMEC   (Belgium)

Author keywords

Interconnects; On chip; S parameters; Signal integrity; Validation

Indexed keywords

COMPUTER AIDED LOGIC DESIGN; COMPUTER SIMULATION; CROSSTALK; SCATTERING PARAMETERS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; SPURIOUS SIGNAL NOISE; TRANSMISSION LINE THEORY;

CROSSTALK SIMULATIONS; EXPERIMENTAL VALIDATION; ON-CHIP INTERCONNECTS; SIGNAL INTEGRITY;

MICROPROCESSOR CHIPS;

EID: 13944267488     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2004.841672     Document Type: Article

References (3)

1. D. M. Pozar, [i#Microwave Engineering#1i], 2nd ed. New York: Wiley, 1998.
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3. W. Eisenstadt and Y. Eo, "S-parameter-based IC interconnect transmission line characterization," [i#IEEE Trans. Comp., Hybrids, Manufact. Technol.#1i], vol. 15, no. 4, pp. 483-483, Aug. 1992.