Low temperature fabrication of poly-Si FEA for display application

Technical Digest of the 17th International Vacuum Nanoelectronics Conference, IVNC 2004

Volumn , Issue , 2004, Pages 134-135

  Nagao, M ^a   Sacho, Y ^a   Kanemaru, S ^a   Matsukawa, T ^a   Itoh, J ^a  

^a NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONS; ETCHING; FINITE ELEMENT METHOD; GLASS; INTEGRATION; LOW TEMPERATURE EFFECTS; MOSFET DEVICES; OXIDATION; PHOTORESISTS; PROBABILITY; SILICON WAFERS; SPUTTERING;

EMISSION CURRENT; GATE HOLE; ION ETCHING; ION SPUTTERING;

POLYSILICON;

EID: 13644252413     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. T. Sato et al., JVST, B21, p.1589 (2003).
2. T. Asano and T. Tamon, Technical Digest of 4th IVMC, p.88 (1991).