DUV optical wafer inspection system for 65-nm technology node

Hitachi Review

Volumn 54, Issue 1, 2005, Pages 22-26

  Watanabe, Kenji ^a   Maeda, Shunji ^b   Funakoshi, Tomohiro ^a   Miyazaki, Yoko ^c  

^a HITACHI HIGH TECHNOLOGIES CORPORATION   (Japan)

^b Prod Eng Research Laboratory   (Japan)

^c Development Department   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DEEP ULTRAVIOLET (DUV) OPTICAL WAFER INSPECTION SYSTEMS; GATE INSULATION; MASS PRODUCTION; MINIATURIZATION; OPTICAL PROXIMITY CORRECTION (OPC); PROCESS NODE;

ABERRATIONS; ALGORITHMS; GATES (TRANSISTOR); IMAGE PROCESSING; NOISE ABATEMENT; PHOTORESISTS; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS; ULTRAVIOLET DEVICES;

INSPECTION EQUIPMENT;

EID: 13544254532     PISSN: 0018277X     EISSN: 0018277X     Source Type: Trade Journal    
DOI: None     Document Type: Review

References (1)

1. Hyunjo Yang et al., "OPC Accuracy and Process Window Verification Methodology for Sub-100 nm Nodes," SPIE (2004).