An 88-way multiprocessor within an fpga with customizable instructions

Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM)

Volumn 18, Issue , 2004, Pages 3537-3544

  Hoare, Raymond ^a   Tung, Shenchih ^a   Werger, Katrina ^a  

^a PA 15260   (United States)

Author keywords

Architecture; DSP; FPGA; Parallelism; SIMD

Indexed keywords

COMPUTER ARCHITECTURE; DATA ACQUISITION; DATA REDUCTION; DIGITAL SIGNAL PROCESSING; EFFICIENCY; FIELD PROGRAMMABLE GATE ARRAYS; FORMAL LOGIC; PARALLEL PROCESSING SYSTEMS; RESOURCE ALLOCATION;

ARITHMETIC LOGIC UNIT (ALU); DSP; PARALLELISM; SIMD;

MULTIPROCESSING SYSTEMS;

EID: 12444336901     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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