VLIW across multiple superscalar processors on a single chip

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 1997, Pages 166-175

  Kim, Soohong P ^a   Hoare, Raymond R ^a   Dietz, Henry G ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); COMPUTER ARCHITECTURE; CONSTRAINT THEORY; DATA COMMUNICATION SYSTEMS; MICROPROCESSOR CHIPS; PROGRAM COMPILERS; RESPONSE TIME (COMPUTER SYSTEMS); SYSTOLIC ARRAYS;

INSTRUCTION LEVEL PARALLELISM (ILP); MULTIPLE SUPERSCALAR PROCESSORS; VERY LONG INSTRUCTION WORD (VLIW) ARCHITECTURES;

PARALLEL PROCESSING SYSTEMS;

EID: 0031375505     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)