On the maximum number of DC solutions of general transistor networks

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 2000, Pages 928-931

  Vargas Bernal, Rafael ^a   Sarmiento Reyes, Arturo ^a,b   Hernández Martínez, Luis ^a  

^a UNIVERSITY OF GUANAJUATO   (Mexico)

^b INSTITUTO NACIONAL DE ASTROFÍSICA   (Mexico)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT SOURCES; LINEAR RESISTORS; TOPOLOGICAL CONDITIONS; UPPER BOUND;

TOPOLOGY;

EID: 1242318222     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2000.913028     Document Type: Conference Paper

References (6)

1. L. A. Sarmiento Reyes, A Partition Method for the Determination of Multiple DC Operating Points, Ph.D. thesis, Delft University of Technology, May 1994.
2. A. Sarmiento-Reyes, "A Novel Method to predict both, the Upper Bound on the Number and the Stability of DC Operating Points, " in Proc. IEEE Int. Symp. Circuits Systems, Seattle, WA, USA, 1995, vol.1, pp. 101-104.
3. B. G. Lee and A. N. Willson, "All Two-Transistor Circuits possess at most Three DC Equilibrium Points, " in Proc. 26th Midwest Symp. Circuits Systems, Puebla, Mexico, 1983, pp. 504-507.
4. J. C. Lagarias and L. Trajkovic, "Bounds for the Number of DC Operating Points of Transistor Circuits, " IEEE Trans. Circuits Syst. I, vol.46, no.10, pp. 1216-1221, October 1999.
5. R. Vargas-Bernal and A. Sarmiento-Reyes, "A Topology-based Method for Identifying Flip-flops Graphs in BJT Circuits, " in Proc. IEEE Int. Symp. Circuits Systems, Orlando, FL, USA, 1999, vol.6, pp. 133-136.
6. R. Vargas-Bernal, Assessing the Uniqueness and Upper Bound of the DC Solutions with Circuit Topology, Ph.D. thesis, National Institute of Astrophysics Optics and Electronics (INAOE), Puebla, Mexico, July 19th, 2000.