New redundancy identification on logic optimization using implication relations

Technology Reports of the Osaka University

Volumn 48, Issue 2301-2318, 1998, Pages 55-63

  Ichihara, Hideyuki ^a   Kinoshita, Kozo ^a  

^a Department of Applied Physics ^*

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK SYNTHESIS; IDENTIFICATION (CONTROL SYSTEMS); OPTIMIZATION; REDUNDANCY;

LOGIC OPTIMIZATION; REDUNDANT FAULTS; TEST PATTERN GENERATION METHODS;

LOGIC CIRCUITS;

EID: 11644253336     PISSN: 00306177     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (9)

1. M. Abramovici and M. A. Iyer, "One-Pass Redundancy Identification and Removal," Proc. Int'l Test Conf. (1992) pp. 807-815.
2. S. C. Chang and M. M. Sadowska, "Perturb and Simplify: Multi-level Boolean Network Optimizer," Int'l Conf. on CAD (1994) pp. 2-5.
3. W. Kunz and P. R. Menon, "Multi-Level Logic Optimization by Implication Analysis," Int'l Conf. on CAD (1994) pp. 6-13.
4. Entrena L. A. and Cheng K. T, "Sequential Logic Optimization by Redundancy Addition and Removal," Proc. Int'l Conf on CAD (1993) pp. 310-315.
5. R. K. Brayton, R. Rudell, A Sangiovanni-Vincentelli and A. R. Wang, "MIS: Multi-level Interactive Logic Optimization System," IEEE Trans. on CAD (1987) pp. 1062-1081.
6. W. Kunz and P. R. Menon, "Recursive Learning: An Attractive Alternative to the Decision Tree for Test Generation in Digital Circuits," Proc. Int'l Test Conf. (1992) pp. 816-825.
7. M. A. Iyer and M. Abramovici, "Low-Cost Redundancy Identification for Combinational Circuits," Proc. 7th. Int'l Conf. on VLSI Design, India (1994) pp. 315-318.
8. M. Abramovici, J. J. Kulikowski and R. K. Roy, "The Best Flip-Flops to Scan," Proc. Int'l Test Conf. (1991) pp. 166-173."
9. H. Ichihara and K. Kinoshita, "On Acceleration of Logic Circuits Optimization using Implication Relations," The Sixth Asian Test Symposium (1997).