On acceleration of logic circuits optimization using implication relations

Proceedings of the Asian Test Symposium

Volumn , Issue , 1997, Pages 222-227

  Ichihara, Hideyuki ^a   Kinoshita, Kozo ^a  

^a OSAKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

IMPLICATION RELATIONS; MULTILEVEL LOGIC OPTIMIZATION METHOD; REDUNDANCY IDENTIFICATION METHOD;

COMPUTATIONAL METHODS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; OPTIMIZATION;

COMBINATORIAL CIRCUITS;

EID: 0031377636     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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2. S. C. Chang and M. M. Sadowska, "Perturb and Simplify: Multi-level Boolean Network Optimizer, " Int'l Conf on CAD, pp. 2-5, 1994.
3. W. Kunz and P. R. Menon, "Multi-Level Logic Optimization by Implication Analysis, " Int'l Conf on CAD, 1994.
4. W. Kunz and P. R. Menon, "Recursive Learning: An Attractive Alternative to the Decision Tree for Test Generation in Digital Circuits, " Proc. Int'l Test Conf, pp. 816-825, 1992.
5. M. A. Iyer and M. Abramovici, "Low-Cost Redundancy Identification for Combinational Circuits, " Proc. 7th. Int'l. Conf. on VLSI Design, India, pp. 315-318, 1994.
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7. Hideyuki Ichihara, Seiji Kajihara and Kozo Ki-noshita, "On Invariant Implication Relations for Removing Partial Circuits, " IEICE Trans. D-I, Vol. J79-D-I, No. 12, pp. 1037-1045, 1996 (in Japanese).
8. Michael H. Schulz, Erwin Trischler and Thomas M. Sarfert, "SOCRATES: A Highly Efficient Automatic Test Pattern Generation System, " IEEE Trans. CAD, pp. 126-137, 1988.
9. Hideyuki Ichihara, "On Acceleration of Logic Circuit Optimization using Imphcation Relations, " master's thesis, 1997 (in Japanese).