Semantics and Runtime Monitoring of TLCharts: Statechart Automata with Temporal Logic Conditioned Transitions

Electronic Notes in Theoretical Computer Science

Volumn 113, Issue SPEC. ISS., 2005, Pages 3-21

  Drusinsky, Doron ^a  

^a Naval Postgraduate School   (United States)

Author keywords

Finite automata; Formal specification; Harel Statecharts; Semantics; Temporal logic

Indexed keywords

FORMAL SPECIFICATION; HAREL STATECHARTS; LINEAR-TIME TEMPORAL LOGIC (LTL); RUN TIME; TEMPORAL LOGIC;

COMPUTER SCIENCE; COMPUTER SOFTWARE; FINITE AUTOMATA; FORMAL LANGUAGES; HIERARCHICAL SYSTEMS; LARGE SCALE SYSTEMS;

SEMANTICS;

EID: 11344256570     PISSN: 15710661     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.entcs.2004.01.025     Document Type: Conference Paper

References (21)

1. R. Alur, and D. Dill A Theory of Timed Automata Theoretical Computer Science 126 1994 183 235
2. G.S. Avrunin, J.C. Corbett, and M.B. Dwyer, Property Specification Patterns for Finite-State Verification, 2nd Workshop on Formal Methods in Software Practice, March 1998
3. B. Bruegge, Object-Oriented Software Engineering: Conquering Complex and Changing Systems, Prentice Hall, ISBN 0-13-489725-0
4. E. Chang, A. Pnueli, and Z. Manna Compositional Verification of Real-Time Systems Proc. 9'th IEEE Symp. On Logic In Computer Science 1994 458 465
5. D. Drusinsky, On Synchronized Statecharts, Ph.D. Dissertation, Weizmann Institute of Science, 1988
6. D. Drusinsky, Monitoring Temporal Rules Combined with Time Series, Proc. 2003 Computer Aided Verification Conference (CAV), pp. 114-117.
7. D. Drusinsky, Visual Formal Specification using (N)TLCharts: Statechart Automata with Temporal Logic and Natural Language Conditioned Transitions. International Workshop on Parallel and Distributed Systems: Testing and Debugging (PADTAD), 2004
8. D. Drusinsky Specs Can Handle Exceptions Embedded Developers Journal November 2001 10 14
9. D. Drusinsky, The Temporal Rover and the ATG Rover. Proc. SPIN 2000 Workshop. Springer Verlag Lecture Notes in Computer Science, 1885, p. 323-329
10. D. Drusinsky A State Assignment for Single-block Implementation of Statecharts IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10 12 December 1991 1569 1575
11. D. Drusinsky, and David Harel On the Power of Bounded Concurrency I: Finite Automata Journal of the ACM 41 3 May 1994 517 539
12. D. Harel Statecharts: A Visual Formalism for Complex Systems Science of Computer Programming 8 1987 231 274
13. D. Harel, and A. Naamad The Statemate Semantics of Statecharts ACM Tran. of Software Engineering and Methodology 5 4 Oct 1996
14. C. Eisner, D. Fishman, J. Havlicek, Y. Lustig, A. McIsaac, D. Van Campenhout, Reasoning with Temporal Logic on Truncated Paths, Proc. 2003 Computer Aided Verification Conference (CAV), pp. 27-39
15. M. Enciso, I.P. de Guzm'an, and C. Rossi Using Temporal Logic to Represent Dynamic Behaviour of UML Statecharts ECOOP 2002 Workshop on Integration and Transformation of UML Models 2002
16. J. Hopcroft, and J. Ullman Theory of Formal Languages and Automata 2'nd edition 2001 Addison Wesley ISBN 0-201-44124-
17. Kahanna, C.A., Statecharts with Overlapping States, M.S. Thesis, Dept. of Mathematics and Computer Science, Bar-Ilan University, Ramat-Gan, Israel, 1986 (in Hebrew)
18. Z. Manna, and A. Pnueli Verification of Concurrent Programs: Temporal Proof Principles Proc. of the Workshop on Logics of Programs LNCS 1981 Springer 200 252
19. A. Pnueli The Temporal Logic of Programs Proc. 18'th IEEE Symp. on Foundations of Computer Science 1977 46 57
20. J. Rumbaugh, M. Blaha, W. Premerlani, E. Frederick, W. Lorensen, Object Oriented Modeling and Design, Prentice Hall, ISBN 0-13-629841-9
21. S.R. Sowmya, and S. Ramesh Extending Statecharts with Temporal Logic IEEE Transactions on Software Engineering 24 3 March 1998-1998