Parallel architecture for video processing in a smart camera system

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn , Issue , 2002, Pages 9-14

  Lv, T ^a   Ozer, B ^a   Wolf, W ^a  

^a Princeton University   (United States)

Author keywords

Algorithm design and analysis; Computer architecture; Data analysis; Hardware; Humans; Parallel architectures; Parallel processing; Real time systems; Smart cameras; VLIW

Indexed keywords

CAMERAS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DATA REDUCTION; INTERACTIVE COMPUTER SYSTEMS; PARALLEL PROCESSING SYSTEMS; REAL TIME SYSTEMS; SIGNAL PROCESSING; VERY LONG INSTRUCTION WORD ARCHITECTURE; VIDEO SIGNAL PROCESSING;

ALGORITHM DESIGN AND ANALYSIS; HUMANS; PARALLEL PROCESSING; SMART CAMERAS; VLIW;

PARALLEL ARCHITECTURES;

EID: 11244333607     PISSN: 15206130     EISSN: None     Source Type: Journal    
DOI: 10.1109/SIPS.2002.1049677     Document Type: Article

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