Area/delay estimation for digital signal processor cores

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2001-January, Issue , 2001, Pages 156-161

  Miyaoka, Y ^a   Kataoka, Y ^a,b   Togawa, N ^a   Yanagisawa, M ^a   Ohtsuki, T ^a  

^a WASEDA UNIVERSITY   (Japan)

^b PANASONIC CORPORATION   (Japan)

Author keywords

Application software; Delay estimation; Digital signal processors; Equations; Estimation error; Hardware; Kernel; Registers; Signal synthesis; Software systems

Indexed keywords

APPLICATION PROGRAMS; COMPUTER AIDED DESIGN; COMPUTER HARDWARE; COMPUTER SOFTWARE; ERRORS; HARDWARE; PROGRAM PROCESSORS; SIGNAL PROCESSING; TIME DELAY;

DELAY ESTIMATION; EQUATIONS; ESTIMATION ERRORS; KERNEL; REGISTERS; SIGNAL SYNTHESIS; SOFTWARE SYSTEMS;

DIGITAL SIGNAL PROCESSORS;

EID: 11244314336     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2001.913297     Document Type: Conference Paper

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