Performance maximization algorithm to design ASIPs under the constraint of chip area including RAM and ROM sizes

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 1998, Pages 367-372

  Binh, Nguyen Ngoc ^a   Imai, Masaharu ^a   Takeuchi, Yoshinori ^a  

^a OSAKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; OPTIMIZATION; RANDOM ACCESS STORAGE; ROM;

APPLICATION SPECIFIC INTEGRATED PROCESSORS (ASIP); HARDWARE-SOFTWARE PARTITIONING;

MICROPROCESSOR CHIPS;

EID: 0032218642     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (19)