Realization of compact low-power ripple-flash A/D converter architectures using conventional digital CMOS technology

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn 2002-January, Issue , 2002, Pages 71-74

  Baumgartner, Renato ^a   Leblebici, Yusuf ^b  

^a RF Integration Inc   (United States)

^b EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; ELECTRIC LOSSES;

CASCADE-CONNECTED; CONVENTIONAL APPROACH; DIFFERENTIAL OUTPUT; DIGITAL CMOS TECHNOLOGY; LOW-POWER DISSIPATION; OUTPUT RESPONSE; SAMPLING FREQUENCIES; SIMPLE OPERATION;

MEMORY ARCHITECTURE;

EID: 11244255992     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASIC.2002.1158033     Document Type: Conference Paper

References (3)

1. R. Baumgartner et ah, "A novel capacitive circuit architecture for compact realization of flash analog-digital converters," Proceedings of 1999 European Conference on Circuit Theory and Design, August 1999, Stresa, Italy.
2. B. Onat et al., "Implementation of a charge-based neural Euclidian classifier for a 3-bit flash analog-to-digital converter," IEEE Transactions on Instrumentation and Measurement, vol. 46, pp. 672-677, June 1997.
3. A. Schmid et al., "A novel analog-digital flash converter architecture based on capacitive threshold logic gates," Proceedings of 1999 IEEE International Symposium on Circuits and Systems, May 1999, Orlando, FL.