Eliminating exception constraints of Java programs for IA-64

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn 2002-January, Issue , 2002, Pages 259-268

  Ishizaki, K ^a   Inagaki, T ^a   Komatsu, H ^a   Nakatani, T ^a  

^a IBM RESEARCH   (United States)

Author keywords

Hardware; Java; Laboratories; Program processors; Registers; Runtime; Safety

Indexed keywords

ACCIDENT PREVENTION; BENCHMARKING; COMPUTER HARDWARE; COMPUTER SOFTWARE; DISTRIBUTED COMPUTER SYSTEMS; FAULTING; HARDWARE; LABORATORIES; PARALLEL ARCHITECTURES; PARALLEL PROCESSING SYSTEMS; PROGRAM COMPILERS; PROGRAM PROCESSORS;

CRITICAL PATH LENGTHS; DIRECT ACYCLIC GRAPHS; JAVA; JUST IN TIME COMPILERS; POTENTIAL REDUCTION; REGISTER PRESSURE; REGISTERS; RUNTIMES;

JAVA PROGRAMMING LANGUAGE;

EID: 11144345504     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2002.1106025     Document Type: Conference Paper

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