FPGA implementation of a probabilistic neural network for a bioelectric human interface

Midwest Symposium on Circuits and Systems

Volumn 3, Issue , 2004, Pages

  Bu, Nan ^a   Hamamoto, Taiji ^a   Tsuji, Toshio ^a   Fukuda, Osamu ^b  

^a HIROSHIMA UNIVERSITY   (Japan)

^b NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ELECTROENCEPHALOGRAPHY; FIELD PROGRAMMABLE GATE ARRAYS; HUMAN COMPUTER INTERACTION; PATTERN RECOGNITION; PERSONNEL TRAINING; PROBABILITY DISTRIBUTIONS; STATISTICAL METHODS;

GAUSSIAN MIXTURE MODEL (GMM); PATTERN DISCRIMINATION; PROBABILISTIC NEURAL NETWORKS (PNN);

NEURAL NETWORKS;

EID: 11144312566     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. D.F. Specht, "Probabilistic Neural Networks," Neural Networks, vol. 3, no. 1, pp. 109-118, 1990.
2. T. Tsuji, O. Fukuda, H. Ichinobe, M. Kaneko, "A Log-Linearized Gaussian Mixture Network and Its Application to EEG Pattern Classification," IEEE Transactions on Systems, Man, and Cybernetics-Part C: Application and Reviews, vol. 29, no. 1, pp. 60-72, 1999.
3. G.D. Zhang, "Neural Network for classification: A Survey," IEEE Transaction on Systems, Man and Cybernetics Part C, vol. 30, no. 4, pp. 451-462, 2000.
4. O. Fukuda, T. Tsuji and M. Kaneko, "An EMG Controlled Robotic Manipulator Using Neural Networks," Proc. of IEEE International Workshop on Robot and Human Communication, pp. 442-447, 1997.
5. O. Fukuda, T. Tsuji, and M. Kaneko, "An EMG-Controlled Pointing Device Using a Neural Network," Proc. of the 1999 IEEE Int. Conf. on Systems, Man, and Cybernetics, vol. 4, pp. 63-68, Tokyo, 1999.
6. O. Fukuda, T. Tsuji, M. Kaneko, and A. Ohtsuka, "A Human-Assisting Manipulator Teleoperated by EMG Signals and Arm Motions," IEEE Trans. on Robotics and Automation, vol. 19, no. 2, pp. 210-222, 2003.
7. M. Porrmann, U. Witkowski, H. Kalte and U. Rückert, "Implementation of Artificial Neural Networks on a Reconfigurable Hardware Accelerator," Proc. of 10th Euromicro Workshop on Parallel, Distributed and Network-based Processing, pp. 243-250, Gran Canada Island, Spain, 2002.
8. D. Anguita, A. Boni, and S. Ridella, "A Digital Architecture for Support Vector Machines: Theory, Algorithm, and FPGA Implementation," IEEE Trans. Neural Networks, vol. 14, no. 5, pp. 993-1009, 2003.
9. A. Bermak, and D. Martinez, "A Compact 3-D VLSI Classifier Using Bagging Threshold Network Ensembles," IEEE Trans. Neural Networks, vol. 14, no. 5, pp. 1097-1109, 2003.
10. S. Haykin, "Neural Networks: A Comprehensive Foundation," Second Edition, Prentice Hall, 1998.
11. R. Andraka, "A Survey of CORDIC Algorithms for FPGA based Computers," Proc. of 1998 ACM/SIGDA 6th Int. Sym. on Field Programmable Gate Arrays, pp. 191-200, Monterey, CA, 1998.
12. A. Meyer-Bäse, R. Watzel, U. Meyer-Bäse, and S. Foo, "A parallel CORDIC architecture dedicated to compute the Gaussian potential function in neural networks," Engineering Applications of Artificial Intelligence, vol. 16, no. 7-8, pp. 595-605, 2003.
13. S.M. Loo, B.E. Wells, N. Freije, and J. Kulick, "Handel-C for Rapid Prototyping of VLSI Coprocessors for Real Time Systems," Proc. of 34th IEEE Southeastern Symposium on System Theory, pp. 6-10, Huntsville, AL, 2002.