Targeted Defect Analysis for Yield Improvement

Conference Proceedings from the International Symposium for Testing and Failure Analysis

Volumn , Issue , 2002, Pages 571-577

  Andrade, Luis ^a   Bynum, Timothy ^a   Doyle, Richard ^a   Fiaherty, Brian ^a   Grammer, David ^a   Jacobs, Chris ^a   Luzar, Mark ^a   McDaniel, Eric ^a   Ricks, Dave ^a   Stanley, Randall ^a   Taylor, Tom ^a  

^a INFINEON TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CORRELATION METHODS; ELECTRIC LOSSES; FAILURE ANALYSIS; PROCESS ENGINEERING; SILICON WAFERS;

DEFECT ENGINEERING; TARGETED DEFECT ANALYSIS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 10744220610     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. R. Ott, H. Ollendorf, H. Lammering, T. Hladschik, W. Haensch, IEEE/SEM/Advanced Semiconductor Manufacturing Conference, p 87-91 (1999)
2. Compressed Bit fail maps for memory fail pattern classification, J. Vollrath, U. Lederer, T. Hladschik, ETW 2000, Informal Digest, pp 207-212