Fault isolation of large nets using bridging fault analysis

Proceedings of the 30th International Symposium for Testing and Failure Analysis, ISTFA 2004

Volumn , Issue , 2004, Pages 99-102

  Ontko, George ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BRIDGING FAULT ANALYSIS; FAULT ISOLATION; LARGE NETS; PASSING VECTOR CORRELATION (PVC);

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CORRELATION METHODS; DEFECTS; ELECTRIC WIRE; FAULT TREE ANALYSIS; FORMAL LOGIC; INTEGRATED CIRCUITS; NONDESTRUCTIVE EXAMINATION; VECTORS;

ELECTRIC FAULT CURRENTS;

EID: 10444275779     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. S. D. Millman and E. J. McCluskey, "Detecting Bridging Faults with Stuck-at Tests Sets," IEEE International Test Conference 1988, pp. 773-783
2. N. A. Touba and E. J. McCluskey, "Pseudo-Random Pattern Testing of Bridging Faults," ICCAD 1997, pp. 54-60
3. Y. K. Malaiya, A.P. Jayasumana, "A Detailed Examination of Bridging Faults," in IEEE International Conference on Computer Design, 1986, pp 78-81
4. B. Chess and T. Larrabee, "Logic Testing of Bridging Faults in CMOS Integrated Circuits," IEEE Transactions on Computers, Vol. 47, No. 3, pp 338-345
5. B. Chess, D. B. Lavo, F. J. Ferguson, and T. Larrabee, "Diagnosis of Realistic Bridging Faults with Single Stuck-at Information," ICCAD 1995, pp. 185-192
6. IEEE Std 1149.1-2001, IEEE Standard Test Access Port and Boundary-Scan Architecture
7. M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design. Computer Science Press 1990, pp. 97-98