Stacked-chip packaging: Electrical, mechanical, and thermal challenges

Proceedings - Electronic Components and Technology Conference

Volumn 2, Issue , 2004, Pages 1608-1613

  Awad, Elie ^a   Ding, Hanyi ^a   Graf, Richard S ^a   Maloney, J J ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRICAL PERFORMANCE; MULTIPACKAGING; STACKED CHIPS; SYSTEM ON CHIP (SOC);

COMPUTER SIMULATION; COSTS; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; MULTILAYERS; PRINTED CIRCUIT BOARDS; SEMICONDUCTOR JUNCTIONS; THERMAL EFFECTS;

ELECTRONICS PACKAGING;

EID: 10444252607     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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2. van Kessel, C. G. M., et al., "The Quality of Die-Attachment and Its Relationship to Stresses and Vertical Die-Cracking," Proc. 1983 ECC, pp. 237-244.
3. Pourahmadi, F., et al., "The effect of corner radius of curvature on the mechanical strength of micromachined single-crystal silicon structures," Digest of Technical Papers, Int. Conf. on Solid-State Sensors and Acuators (Transducers '91), San Francisco, CA, June 1991, pp. 197-200.
4. Petersen, K., "Silicon as a Mechanical Material," Proc. of the IEEE, Vol. 70, No. 5, May 1982.
5. th IEEE Semi-Therm. Symp., pp. 160-167.
6. ChipPAC Takes Six Stacked-die CSP to Market," Advanced Packaging, January 2004, p. 10.