Fabrication and parametric study of wafer-level multiple-copper-column interconnect

Proceedings - Electronic Components and Technology Conference

Volumn 2, Issue , 2004, Pages 1251-1255

  Liao, E B ^a   Ang, Simon S ^b   Tay, Andrew A O ^a   Feng, H H ^c   Nagarajan, Ranganathan ^c   Kripesh, Vaidyanathan ^c  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b UNIVERSITY OF ARKANSAS   (United States)

^c INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

MULTI-COPPER-COLUMN (MCC) INTERCONNECTS; SINGLE-COPPER-COLUMN (SCC) INTERCONNECTS; WAFER LEVEL INTERCONNECTS; WIRE BONDING;

COMPUTER SIMULATION; COPPER; ELECTRIC RESISTANCE; ELECTROPLATING; FLIP CHIP DEVICES; PHOTOLITHOGRAPHY; REACTIVE ION ETCHING; SEMICONDUCTOR DEVICE MANUFACTURE; SOLDERED JOINTS; THERMAL CYCLING; THERMOMECHANICAL TREATMENT;

CHIP SCALE PACKAGES;

EID: 10444226510     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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