A new test structure for measuring on-chip cross-coupling capacitances

Proceedings - 8th IEEE Workshop on Signal Propagation on Interconnects

Volumn , Issue , 2004, Pages 165-166

  Bogliolo, Alessandro ^a   Vaira, Fabrizio ^b   Vendrame, Loris ^c   Bortesi, Luca ^c  

^a UNIVERSITY OF URBINO   (Italy)

^b UNIVERSITY OF FERRARA   (Italy)

^c STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CROSSTALK; ELECTRIC INVERTERS; ELECTRIC POTENTIAL; SWITCHING; TRANSDUCERS;

CROSS-COUPLING CAPACITANCES; POWER SUPPLY; SHORT-CIRCUIT CURRENTS; TEST STRUCTURE;

CAPACITANCE;

EID: 10044298481     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. D. Sylvester, et al., "Analytical modeling and characterization of deep-submicrometer interconnect", Proc. of the IEEE, vol. 89, n.5 May 2001, pp.634-664.
2. D. Sylvester, et al., "Investigation of Interconnect Capacitance Characterization Using Charge-Based Capacitive Measurement (CBCM) Technique and ThreeDimensional Simulation," IEEE J. of Solid-State Circuits, Vol. 33, No. 3, 1998, pp. 449-453.
3. L. Vendrame, et al., "Accuracy Assessment and improvement of On-Chip Charge-Based Capacitance Measurements", in Proc. of IEEE SPI Workshop, 2003.
4. A. Bogliolo, et. al., "Charge-based on-chip measurement technique for the selective extraction of cross-coupling capacitances." in Proc. of IEEE SPI Workshop, 2002.