A universal technique for fast and flexible instruction-set architecture simulation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 23, Issue 12, 2004, Pages 1625-1639

  Braun, Gunnar ^a   Nohl, Achim ^a   Hoffmann, Andreas ^a   Schliebusch, Oliver ^b   Leupers, Rainer ^b   Meyr, Heinrich ^b  

^a CoWare Inc ^*  (Germany)

^b RWTH AACHEN UNIVERSITY   (Germany)

Author keywords

Computer architecture; Design automation; Hardware design languages; Modeling; Program processors; Simulation software; Software prototyping

Indexed keywords

BUFFER STORAGE; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SIMULATION; PROGRAM PROCESSORS; SOFTWARE PROTOTYPING;

DESIGN AUTOMATION; HARDWARE DESIGN LANGUAGES; PROCESSOR COMPLEXITY; SIMULATION SOFTWARE;

COMPUTER SOFTWARE;

EID: 10044231557     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2004.836734     Document Type: Article

References (17)

1. G. E. Moore, "Cramming more components onto integrated circuits," Electronics, vol. 38, pp. 114-117, 1965.
2. C. Mills, S. C. Ahalt, and J. Fowler, "Compiled instruction set simulation," Software - Practice Exper., vol. 21, no. 8, pp. 877-889, 1991.
3. A. Hoffmann, T. Kogel, A. Nohl, G. Braun, O. Schliebusch, A. Wieferink, and H. Meyr, "A novel methodology for the design of application specific instruction set processors (ASIP) using a machine description language," IEEE Trans. Computer-Aided Design, vol. 20, pp. 1338-1354, Nov. 2001.
4. V. Zivojnovic and H. Meyr, "Compiled HW/SW cosimulation," in Proc. Design Automation Conf., June 1996, pp. 690-695.
5. A. Halambi, P. Grun, V. Ganesh, A. Khare, N. Dutt, and A. Nicolau, "EXPRESSION: A language for architecture exploration through compiler/simulator retargetability," in Proc. Conf. Design, Automation, Test Em, Mar. 1999, pp. 485-490.
6. G. Hadjiyiannis, S. Hanono, and S. Devadas, "ISDL: An instruction set description language for retargetability," in Proc. Design Automation Conf., Jun. 1997, pp. 299-302.
7. G. Hadjiyiannis, P. Russo, and S. Devadas, "A methodology for accurate performance evaluation in architecture exploration," in Proc. Design Automation Conf., Jun. 1999, pp. 927-932.
8. Z. Barzilai et al., "HSS - A high-speed simulator," IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 601-616, July 1987.
9. A. Cagney. (1994-1996) PSIM - Model of the PowerPC Architecture. [Online] Available: http://sources.redhat.com/psim/index.html
10. M. Hartoog, J. A. Rowson, P. D. Reddy, S. Desai, D. D. Dunlop, E. A. Harcourt, and N. Khullar, "Generation of software tools from processor descriptions for hardware/software codesign," in Proc. Automation Conf., June 1997, pp. 303-306.
11. R. Leupers, J. Elste, and B. Landwehr, "Generation of interpretive and compiled instruction set simulators," in Proc. Asia South Pacific Design Automation Conf., Jan. 1999, pp. 339-342.
12. F. Engel, J. Nuhrenberg, and G. P. Fettweis, "A generic tool set for application specific processor architectures," in Proc. Int. Workshop Hardware/Software Codesign, Apr. 1999, pp. 126-130.
13. G. Braun, A. Hoffmann, A. Nohl, and H. Meyr, "Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description," in Proc. Int. Symp. Syst. Synthesis, Oct. 2001, pp. 57-62.
14. E. Witchel and M. Rosenblum, "Embra: Fast and flexible machine simulation," in Proc. Int. Conf. Measure. Modeling Comput. Syst., May 1996, pp. 68-79.
15. B. Cmelik and D. Keppel, "Shade: A fast instruction-set simulator for execution profiling," ACM SIGMETRICS Perform. Eval. Rev., vol. 22, no. 1, pp. 128-137, 1994.
16. E. Schnarr and J. R. Larus, "Fast out-of-order processor simulation using memoization," in Proc. 8th Int. Conf. Architect. Support Program. Lang. Oper. Syst., Oct. 1998, pp. 283-294.
17. E. Schnarr, M. D. Hill, and J. R. Larus, "Facile: a language and compiler for high-performance processor simulators," in Proc. Int. Conf. Program. Lang. Design Implement., Oct. 1998, pp. 321-331.