A Novel Leakage Current Separation Technique in a Direct Tunneling Regime Gate Oxide SONOS Memory Cell

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2003, Pages 617-620

  Chung, Steve S ^a   Chiang, P Y ^a   Chou, George ^b   Huang, C T ^b   Chen, Paul ^b   Chu, C H ^b   Hsu, Charles C H ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b EMEMORY TECHNOLOGY INC   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; GROWTH (MATERIALS); INTERFACES (MATERIALS); LEAKAGE CURRENTS; SATURATION (MATERIALS COMPOSITION); SILICA; STRESS ANALYSIS; THERMIONIC EMISSION; TRANSIENTS; VOLTAGE MEASUREMENT;

DIGITAL CAMERAS; SURFACE POTENTIAL;

FLASH MEMORY;

EID: 0842288188     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. D. Kahng and S. M. Sze, Bell System Technical Journal, p. 1288, 1967.
2. M. H. White et al., IEEE Circuits and Devices Magazine, pp. 22-31, 2000.
3. Y. Yang and M. H. White, Solid State Electronics, vol. 44, pp. 948-958, 2000.
4. L. Lundkvist, C. Svensson and B. Hansson, Solid-State Electronics, vol. 10, pp. 221-227, 1976.
5. A. Goda and M. Noguchi, IEEE NVSM Workshop, p. 65, 2003.
6. S. M. Sze, Phys. of Semiconductor Devices, John Wiley, 1981.
7. S. Mori et al, IEEE Trans. on ED., Vol. 43, No 1, pp. 47-53, 1996.
8. Y. Hu and M. H. White, Solid State Electronics, vol. 36, pp. 1401-1416, 1993.