A low-leakage dynamic multi-ported register file in 0.13μm CMOS

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 68-71

  Alvandpour, A ^a   Krishnamurthy, R ^a   Soumyanath, K ^a   Borkar, S ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT THEORY; ELECTRIC POTENTIAL; FILE ORGANIZATION; NOISE ABATEMENT; STATIC ELECTRICITY;

MULTI-PORTED REGISTER FILE;

LEAKAGE CURRENTS;

EID: 0034870071     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/383082.383096     Document Type: Conference Paper

References (6)

1. A conditional keeper technique for sub-0.13μm wide dynamic gates
2. A leakage tolerant multi-phase keeper for wide domino circuit
3. A 0.13μm 6GHZ 256×32b leakage-tolerant register file
4. High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies