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Volumn 39, Issue 1, 2004, Pages 238-241

An 8-bit 2-Gsample/s folding-interpolating analog-to-digital converter in SiGe technology

Author keywords

Analog to digital converter (ADC); Folding interpolating; Heterojunction bipolar transistor (HBT)

Indexed keywords

ANALOG TO DIGITAL CONVERSION; DESIGN FOR TESTABILITY; ELECTRIC POWER SUPPLIES TO APPARATUS; GAIN MEASUREMENT; HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 0742321272     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.820867     Document Type: Article
Times cited : (26)

References (9)
  • 2
    • 0036293010 scopus 로고    scopus 로고
    • A bipolar 2-GSample/s track-and-hold amplifier (THA) in a 0.35 μm SiGe technology
    • F. Vessal and C. A. T. Salama, "A bipolar 2-GSample/s track-and-hold amplifier (THA) in a 0.35 μm SiGe technology," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 5, 2002, pp. 573-576.
    • (2002) Proc. IEEE Int. Symp. Circuits and Systems , vol.5 , pp. 573-576
    • Vessal, F.1    Salama, C.A.T.2
  • 4
    • 84866895249 scopus 로고    scopus 로고
    • An 8-bit, 1-GSample/s folding-interpolating analog-to-digital converter
    • W. An and C. A. T. Salama, "An 8-bit, 1-GSample/s folding-interpolating analog-to-digital converter," in Proc. Eur. Solid-State Circuits Conf., 2000, pp. 200-203.
    • Proc. Eur. Solid-State Circuits Conf., 2000 , pp. 200-203
    • An, W.1    Salama, C.A.T.2
  • 7
    • 0035696160 scopus 로고    scopus 로고
    • A 6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS
    • M. Choi and A. A. Abidi, "A 6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS," IEEE J. Solid-State Circuits, vol. 36, pp. 1847-1858, 2001.
    • (2001) IEEE J. Solid-State Circuits , vol.36 , pp. 1847-1858
    • Choi, M.1    Abidi, A.A.2
  • 8
    • 0036917305 scopus 로고    scopus 로고
    • A 6-b 1.6-Gsamples/s flash ADC in 0.18-μm CMOS using averaging termination
    • P. C. S. Scholtens and M. Vertregt, "A 6-b 1.6-Gsamples/s flash ADC in 0.18-μm CMOS using averaging termination," IEEE J. Solid State Circuits, vol. 37, pp. 1599-1609, 2002.
    • (2002) IEEE J. Solid State Circuits , vol.37 , pp. 1599-1609
    • Scholtens, P.C.S.1    Vertregt, M.2
  • 9
    • 0036544662 scopus 로고    scopus 로고
    • Speed-power accuracy tradeoff in high-speed CMOS ADCs
    • K. Uyttenhove and M. S. J. Steyaert, "Speed-power accuracy tradeoff in high-speed CMOS ADCs," IEEE Trans. Circuits Syst, II, vol. 49, pp. 280-287, 2002.
    • (2002) IEEE Trans. Circuits Syst, II , vol.49 , pp. 280-287
    • Uyttenhove, K.1    Steyaert, M.S.J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.