Formal verification for embedded system designs

Design Automation for Embedded Systems

Volumn 8, Issue 2-3, 2003, Pages 139-153

  Chen, Xi ^a   Hsieh, Harry ^a   Balarin, Felice ^b   Watanabe, Yosinori ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

Author keywords

Formal verification; LTL; Meta model; Metropolis; Model checking; SPIN

Indexed keywords

COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SOFTWARE SELECTION AND EVALUATION; FORMAL LANGUAGES; OBJECT ORIENTED PROGRAMMING; SEMANTICS; SYSTEMS ANALYSIS;

FORMAL VERIFICATION; MODEL CHECKING;

EMBEDDED SYSTEMS;

EID: 0347622537     PISSN: 09295585     EISSN: None     Source Type: Journal    
DOI: 10.1023/b:daem.0000003959.60964.4d     Document Type: Article

References (15)

1. SPIN manual, http://netlib.bell-labs.com/netlib/spin/whatispin.html, 2003.
2. SystemC homepage, http://www.systemc.org, 2003.
3. Appel, A. W. Modern Compiler Implementation in Java. Cambridge University Press, 1998.
4. Balarin, F., L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli, M. Sgroi, and Y. Watanabe. Modeling and Designing Heterogeneous Systems. Technical Report 2001/01, Cadence Berkeley Laboratories, November 2001.
5. Balarin, F., Y. Watanabe, J. Burch, L. Lavagno, R. Passerone, and A. Sangiovanni-Vincentelli. Constraints Specification at Higher Levels of Abstraction. International Workshop on High Level Design Validation and Test - HLDVT01, September 2001.
6. Brunel, J., E. A. de Kock, W. M. Kruijtzer, H. J. H. N. Kenter, and W. J. M. Smits. Communication refinement in video systems on chip. Proceedings of the Seventh International Workshop on Hardware! Software Codesign, pp. 142-146, 1999.
7. Gangwal, O., A. Nieuwland, and P. Lippens. A Scalable and Flexible Data Synchronization Scheme for Embedded hw-sw Shared-Memory Systems. International Symposium on System Synthesis, October 2001.
8. Godefroid, P. and G. J. Holzmann. On the verification of temporal properties. Proceedings of IFIP/WG6.1 Symposium on Protocols Specification, Testing, and Verification, June 1993.
9. Holzmann, G. J. The Model Checker SPIN. IEEE Transactions on Software Engineering, vol. 23, no. 5, pp. 279-258, May 1997.
10. Holzmann, G. J. An Analysis of Bitstate Hashing. Formal Methods in Systems Design, vol. 13, no. 3, pp. 289-307, November 1998.
11. Kahn, G. The Semantics of a Simple Language for Parallel Programming. Proceedings of IFIP Congress 74, pp. 471-475, 1974.
12. Keutzer, K., S. Malik, A. R. Newton, J. Rabaey, and A. Sangiovanni-Vincentelli. System Level Design: Orthogonalization of Concerns and Platform-Based Design. IEEE Transactions on Computer-Aided Design, vol. 19, no. 12, pp. 1523-1543, December 2000.
13. Kock, E. d., G. Essink, W. Smits, P. v. d. Wolf, J. Brunei, W. Kruijtzer, P. Lieverse, and K. Vissers. YAPI: Application Modeling for Signal Processing Systems. Proceedings of the 37th Design Automation Conference, 2000.
14. Manna, Z. and A. Pnueli. The Temporal Logic of Reactive and Concurrent Systems: Specification. Springer-Verlag, 1992.
15. McMillan, K. Symbolic Model Checking. Kluwer Academic Publishers, 1993.