Impact of PCI-bus load on applications in a PC architecture

Proceedings - Real-Time Systems Symposium

Volumn , Issue , 2003, Pages 430-438

  Schönberg, Sebastian ^a  

^a DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; DATA HANDLING; DATA STORAGE EQUIPMENT; DATA TRANSFER; INTERFACES (COMPUTER); PERSONAL COMPUTERS; RESPONSE TIME (COMPUTER SYSTEMS);

EXECUTION TIME; INPUT OUTPUT DEVICES; MEMORY BUS;

REAL TIME SYSTEMS;

EID: 0346935068     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

1. The SPEC benchmark suite. http://www.specbench.org.
2. AIM Multiuser Benchmarks. http://www.caldera.com/developers/community/contrib/aim.html. Suite VII and IX of what used to be AIM Technology's benchmarks, GPL-ed.
3. R. Baumgartl, M. Borriss, H. Härtig, C.-J. Hamann, M. Hohmuth, L. Reuther, S. Schönberg, and J. Wolter. Dresden Realtime Operating System. In Proceedings of the First Workshop on System Design Automation (SDA '98), pages 205-212, Dresden, Mar. 1998.
4. F. Bellosa. Process cruise control: Throtteling memory access in a soft real-time environment. Technical Report TR-14-97-02, IMMDV IV, University of Erlangen, July 1997.
5. M. Benson. PBI - PCI Bus Interface. FORE Systems Inc., Nov. 1995.
6. A. B. Brown and M. I. Seltzer. Operating system benchmarking in the wake of lmbench: A case study of the performance of NetBSD on the Intel x86 architecture. In ACM SIGMETRICS Conference on Measurement and Modeling and Computer Systems, pages 214-224, Seattle, WA, June 1997.
7. S. Edgar and A. Burns. Statistical Analysis of WCET for Scheduling. In Proceedings IEEE RTSS 2001, London, UK, Dec. 2001. IEEE/IEE.
8. H. Härtig, R. Baumgartl, M. Borriss, C.-J. Hamann, M. Hohmuth, F. Mehnert, L. Reuther, S. Schönberg, and J. Wolter. DROPS: OS support for distributed multimedia applications. In Proceedings of the Eighth ACM SIGOPS European Workshop, Sintra, Portugal, Sept. 1998.
9. T.-Y. Huang, J. W. Liu, and J.-Y. Chung. Allow Cycle-Stealing Direct Memory Access I/O Concurrent with Hard-Real-Time Programs. In Int. Conf on Parallel and Distributed Systems (ICSPAD), Tokyo, June 1996.
10. Intel Corp., Santa Clara. Intel 430TX PCISET: 82439TX System Controller (MTXC) Reference Manual, Feb. 1997. Order #290559-001.
11. J. Liedtke, H. Härtig, and M. Hohmuth. OS-controlled cache predictability for real-time systems. In Third IEEE Realtime Technology and Applications Symposium (RTAS), pages 213-223, Montreal, Canada, June 1997.
12. D. Ofelt and J. L. Hennessy. Efficient performance prediction for modern microprocessors. In Proceedings of the ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, ACM SIGMETRICS Performance Evaluation Review, pages 229-239, New York, June 2000. ACM Press.
13. B. Peuto and L. Shustek. An instruction timing model of CPU performance. In International Conference on Computer Architecture, 25 years of the international symposia on computer architecture (selected papers), pages 152-165, Barcelona, Spain, 1998. ACM Press, New York, NY, USA.
14. R. Saavedra and A. J. Smith. Analysis of benchmark characteristics and benchmark performance prediction. ACM Transactions on Computer Systems, 14(4):344-384, Nov. 1996.
15. R. H. Saavedra and A. J. Smith. Measuring cache and TLB performance and their effect on benchmark run times. IEEE Trans. on Computer C-44(10):1223-1235, Oct. 1995.
16. S. Schönberg, F. Mehnert, C.-J. Hamann, L. Reuther, and H. Härtig. Performance and bus transfer influences. In First Workshop on PC-based System Performance and Analysis, San Jose, CA, Oct. 1998. ACM.
17. R. Sedgewick. Implementing Quicksort programs. Communications of the ACM, 21(10):847-857, Oct. 1978. See corrigendum [18].
18. R. Sedgewick. Corrigendum: "Implementing Quicksort Programs". Communications of the ACM, 22(6):368-368, June 1979. See [17].
19. United States. National Bureau of Standards. Data Encryption Standard, volume 46 of Federal Information Processing Standards publication. U.S. National Bureau of Standards, Gaithersburg, MD, USA, 1977.