Low power monolithic subsampled phase-locked loop architecture for wireless transceivers

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 1999, Pages

  Hafez, Amr N ^a   Elmasry, M I ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COMPUTER SIMULATION; FREQUENCY SYNTHESIZERS; TRANSCEIVERS; VARIABLE FREQUENCY OSCILLATORS;

PHASE DETECTOR; PHASE NOISE; WIRELESS TRANSCEIVERS;

PHASE LOCKED LOOPS;

EID: 0348152081     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (5)