Delay-related secondary objectives for rectilinear Steiner minimum trees

Discrete Applied Mathematics

Volumn 136, Issue 2-3, 2004, Pages 271-298

  Peyer, Sven ^a   Zachariasen, Martin ^b   Jørgensen, David Grove ^b  

^a UNIVERSITY OF BONN   (Germany)

^b UNIVERSITY OF COPENHAGEN   (Denmark)

Author keywords

Rectilinear Steiner trees; Secondary objectives; VLSI design

Indexed keywords

ALGORITHMS; APPROXIMATION THEORY; CAPACITANCE; COMPUTATIONAL METHODS; ELECTRIC DELAY LINES; HEURISTIC METHODS; OPTIMIZATION; PROBLEM SOLVING; VLSI CIRCUITS;

CRITICAL SIGNAL PATH; RECTILINEAR STEINER TREES; SECONDARY OBJECTS;

TREES (MATHEMATICS);

EID: 0346055616     PISSN: 0166218X     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0166-218X(03)00445-1     Document Type: Conference Paper

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