An embedded merging scheme for H.264/AVC motion estimation

IEEE International Conference on Image Processing

Volumn 1, Issue , 2003, Pages 909-912

  Cho, Chuan Yu ^a   Huang, Shiang Yang ^a   Wang, Jia Shung ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; IMAGE CODING; LAGRANGE MULTIPLIERS; MERGING; MOTION COMPENSATION; OPTIMIZATION; VIDEO SIGNAL PROCESSING; VLSI CIRCUITS;

BLOCK MATCHING; SEARCH ALGORITHMS;

MOTION ESTIMATION;

EID: 0345528933     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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4. Komarek, T. and Pirsch, P., "Array architectures for block matching algorithms", Circuits and Systems for Video Technology, IEEE Transactions on , Vol. 36, Issue. 10, pp. 1301-1308, Oct 1989.
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6. Yuan-Hau Yeh and Chen-Yi Lee, "Scalable VLSI architectures for full-search block matching algorithms", Image Processing, 1996. Proceedings., International Conference on, vol. 1, pp.1035 -1038, 16-19 Sep 1996.
7. Do, V.L. and Yun, K.Y., "A low-power VLSI architecture for full-search block-matching motion estimation", Circuits and Systems for Video Technology, IEEE Transactions on, Vol. 8 Issue. 4, pp. 393-398, Aug 1998.
8. Yeu-Shen Jehng, Liang-Gee Chen and Tzi-Dar Chiueh, "An efficient and simple VLSI tree architecture for motion estimation algorithms", Signal Processing, IEEE Transactions on, Vol. 41, Issue. 2, pp. 889-900, Feb 1993.