Microeconomics of process control in semiconductor manufacturing

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5043, Issue , 2003, Pages 57-71

  Monahan, Kevin M ^a  

^a KLA TENCOR CORPORATION   (United States)

Author keywords

300mm wafers; 90nm design rules; AEC; APC; Economics; Profitability; PWM

Indexed keywords

COST EFFECTIVENESS; INVESTMENTS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PERFORMANCE; PROCESS CONTROL; PRODUCTIVITY;

MICROECONOMICS; SCATTEROMETRY-BASED CD PROCESS WINDOW MONITOR;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0345303754     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.487631     Document Type: Conference Paper

References (5)

1. C. Meade and L. Conway. Introduction to VLSI Systems. Menlo Park: Addison-Wesley, 1980, pp 1-5.
2. K. Itoh. VLSI Memory Chip Design. New York: Springer-Verlag, 2001, pp. 1-99.
3. K. M. Monahan, S. Ashkenaz, X. Chen, P. Lord, M. Merrill, R. Quattrini, and J. Wiley, "Accelerated yield learning in aggressive lithography", Proc. SPIE, Vol. 3998, p. 492 (2000).
4. R. C. Elliott, R. K. Nurani, S.-J. Lee, L. Ortiz, M. Preil, J. G. Shanthikumar, T. Riley, and G. Goodwin, "Sampling plan optimization for detection of lithography and etch CD process excursions", Proc. SPIE 3998, pp. 527 (2000).
5. Metrology sample plan optimization is a value-added service provided by KLA-Tencor Corporation.