Flipping structure: An efficient VLSI architecture for lifting-based discrete wavelet transform

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Volumn 1, Issue , 2002, Pages 383-388

  Huang, Chao Tsung ^a   Tseng, Po Chih ^a   Chen, Liang Gee ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Computer architecture; Convolution; Delay; Discrete wavelet transforms; Filters; Hardware; Image coding; Pipeline processing; Transform coding; Very large scale integration

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; CONVOLUTION; FILTERS (FOR FLUIDS); HARDWARE; IMAGE CODING; INTEGRATED CIRCUIT TESTING; MEMORY ARCHITECTURE; VLSI CIRCUITS; WAVELET TRANSFORMS;

BOUNDARY EXTENSIONS; COMPUTATION COMPLEXITY; DELAY; HARDWARE IMPLEMENTATIONS; LIFTING-BASED DISCRETE WAVELET TRANSFORMS; MEMORY REQUIREMENTS; PIPELINE PROCESSING; TRANSFORM CODING;

DISCRETE WAVELET TRANSFORMS;

EID: 0345299382     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APCCAS.2002.1114975     Document Type: Conference Paper

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