High performance 0.2 μm dual gate complementary MOS technologies by suppression of transient-enhanced-diffusion using rapid thermal annealing

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 37, Issue 3 SUPPL. B, 1998, Pages 1054-1058

  Nishida, Yukio ^a   Sayama, Hirokazu ^a   Shimizu, Satoshi ^a   Kuroi, Takashi ^a   Furukawa, Akihiko ^a   Teramoto, Akinobu ^a   Uchida, Tetsuya ^a   Inoue, Yasuo ^a   Nishimura, Tadashi ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

Channel engineering; Dual gate CMOS; MOSFET; Point defect; Rapid thermal annealing; Silicon; Transient enhanced diffusion

Indexed keywords

EID: 0344936955     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.37.1054     Document Type: Article

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