ULSI shallow trench isolation process through the integration of multilayered dielectric process and chemical-mechanical planarization

Thin Solid Films

Volumn 347, Issue 1-2, 1999, Pages 248-252

  Lin, C F ^a,b   Tseng, W T ^c   Feng, M S ^a   Wang, Y L ^d  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b WINBOND ELECTRONICS CORPORATION   (Taiwan)

^c NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^d TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; DIELECTRIC MATERIALS; MULTILAYERS; NITRIDES; OXIDATION; OXIDES; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; SILICON COMPOUNDS; STOICHIOMETRY; ULSI CIRCUITS;

CHEMICAL MECHANICAL PLANARIZATION; CHEMICAL MECHANICAL POLISH; QUARTER MICRON REGIME; SHALLOW TRENCH ISOLATION; SILICON LOCAL OXIDATION;

THIN FILMS;

EID: 0344374453     PISSN: 00406090     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0040-6090(99)00029-2     Document Type: Article

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