Efficient input support selection for sub-functions in functional decomposition based on information relationship measures

Conference Proceedings of the EUROMICRO

Volumn 1, Issue , 1999, Pages 94-101

  Rawski, Mariusz ^a   Jozwiak, Lech ^b   Luba, Tadeusz ^a  

^a WARSAW UNIVERSITY OF TECHNOLOGY   (Poland)

^b EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CLASSICAL METHODS; DECISION SYSTEMS; FUNCTIONAL DECOMPOSITION; HIGH-QUALITY SOLUTIONS; MODERN ENGINEERING; SEQUENTIAL LOGIC; SYSTEMATIC METHOD; SYSTEMATIC SEARCHES;

HEURISTIC METHODS; INFORMATION SCIENCE; OPTIMIZATION;

INTELLIGENT NETWORKS;

EID: 0343895710     PISSN: 10896503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EURMIC.1999.794453     Document Type: Conference Paper

References (24)

1. Brzozowski J. A., Luba T.: Decomposition of Boolean Functions Specified by Cubes, Part 1: Theory of Serial Decompositions Using Blankets, Research Report CS-97-01, University of Waterloo, Waterloo, Canada, 1997; REVISED October 1998
2. Burns M., Perkowski M., Jozwiak L.: An Efficient Approach to Decomposition of Multi-Output Boolean Functions with Large Set of Bound Variables, EUROMICRO'98 Conference, Vasteras, Sweden, 1998
3. Chang S.C., Marek-Sadowska M., Hwang T.T.: Technology Mapping for TLU FPGAs Based on Decomposition of Binary Decision Diagrams, IEEE Trans, on CAD, vol.15, No. 10, October, 1996, pp. 1226-1236.
4. Files C, Perkowski M.: Multi-Valued Functional Decomposition as a Machine Learning Method, ISMVL'98, Fukuoka, Japan, 1998, pp. 173-178.
5. Hartmanis J., Stearns R.E.: Algebraic Structure Theory of Sequential Machines. Prentice-Hall, 1966.
6. Jozwiak L.: General Decomposition And Its Use in Digital Circuit Synthesis, VLSI Design: An International Journal of Custom-Chip Design Simulation and Testing, Special Issue on Decomposition in VLSI Design, vol.3, Nos.3-4, 1995, pp. 225-228.
7. Jozwiak L.: Information Relationships and Measures: An Analysis Apparatus for Efficient Information System Synthesis, 23rd EUROMICRO Conference, Budapest, Hungary, Sept. 1-4, 1997, pp. 13-23
8. Jozwiak L., Konieczny P.: Input Support Minimization for Efficient PLD and FPGA Synthesis. Proc. International Workshop on Logic and Architecture Synthesis, pp. 30-32, 1996.
9. Lai Y.T., Pan K.R.R., Pedram M.: OBDD-Based Functional Decomposition: Algorithm and Implementation, IEEE Trans, on CAD, vol. 15, No 8, August, 1996, pp. 977-990.
10. Luba T., Selvaraj H, Nowicka M. and Kraoeniewski A.: Balanced multilevel decomposition and its applications in FPGA-based synthesis, in G. Saucier, A.Mignotte (ed.), Logic and Architecture Synthesis, Chapman&Hall, 1995.
11. Luba T., Selvaraj H: A General Approach to Boolean Function Decomposition and its Applications in FPGA-based Synthesis. VLSI Design, Special Issue on Decompositions in VLSI Design, vol. 3, Nos. 3A, pp. 289300,1995.
12. Luba T.: Decomposition of Multiple-Valued Functions. 25th International Symposium on Multiple-Valued Logic, Bloomington, Indiana, pp. 256-261,1995.
13. Luba T., Nowicka M. and Rawski M.: Performance-oriented Synthesis for LUT-based FPGAs, Proc. Mixed Design of Integrated Circuits and Systems, pp. 96-101, Lodz, 1996.
14. Venkatesan M., Selvaraj H, Bignall R.: Character Recognition using Functional Decomposition, International Conference on Computational Intelligence and Multimedia Applications, H. Selvaraj, B. Verma eds., pp. 721-726, World Scientific, Singapore 1998.
15. Nowicka M., Luba T., Selvaraj H: Multilevel Decomposition Strategies in Decomposition-Based Algorithms and Tools, Proc. International Workshop on Logic and Architecture Synthesis, pp. 129-136, Grenoble, 1997.
16. Perkowski M., Marek-Sadowska M., Jozwiak L., Luba T., Grygiel S., Nowicka M., Malvi R., Wang Z., Zhang S.: Decomposition of Multiple-Valued Relations, International Symposium on Multiple-Valued Logic, pp. 13-18, Antigonish, Nova Scotia, Canada 1997.
17. Rawski M., Jozwiak L., Nowicka M., Luba T.: Non-Disjoint Decomposition of Boolean Functions and Its Application in FPGA-oriented Technology Mapping, Proc. of the EUROMICRO'97 Conference, Budapest, Hungary, Sept. 1-4, 1997, pp.24-30, IEEE Computer Society Press.
18. Rawski M., Jozwiak L., Luba T.: The Influence of the Number of Values in Sub-functions on the Effectiveness and Efficiency of the Functional Decomposition, EUROMICRO'99 Conference, Milan, Italy, 1999.
19. Ross T., Noviskey M., Taylor T., Gadd D.: Pattern Theory: An Engineering Paradigm for Algorithm Design, Final Technical Report, Wright Laboratories, WL/AART/WPAFB, 1991.
20. Volf F.A.M., Jozwiak L., Stevens M.: General Decomposition And Its Use in Digital Circuit Synthesis, VLSI Design: An International Journal of Custom-Chip Design Simulation and Testing, Special Issue on Decomposition in VLSI Design, vol.3, Nos.3-4, 1995, pp. 225-228.
21. Volf F. A.M., Jozwiak L.: Decompositional Logic Synthesis Approach for Look-up Table Based FPGAs. 8-th IEE International ASIC Conference-ASIC'95, Austin, Texas, September, 1995.
22. Zupan, B, Bohanec M.: Experimental Evaluation of Three Partition Selection Criteria for Decision Table Decomposition, Research Report, Department of Inteligent Systems, Josef Stefan Institute, Ljubljana, Slovenia, Oct. 1966.
23. Zupan B, Bohanec M.: Learning Concept Hierarchies from Examples by Functional Decomposition, Research Report, Department of Inteligent Systems, Josef Stefan Institute, Ljubljana, Slovenia, Sept. 1966.
24. Collaborative Benchmarking Laboratory, Department of Computer Science at North Carolina State University, http://www.cbl.ncsu.edu/