A comparative study of CMOS circuit design styles for low-power high-speed VLSI circuits

International Journal of Electronics

Volumn 84, Issue 6, 1998, Pages 599-613

  Bisdounis, L ^a   Gouvetas, D ^a   Koufopavlou, O ^a  

^a UNIVERSITY OF PATRAS   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0343128121     PISSN: 00207217     EISSN: 13623060     Source Type: Journal    
DOI: 10.1080/002072198134454     Document Type: Article

References (24)

1. Bellaouar, A., and Elmasry, M., 1995, Low-Power Digital VLSI Design: circuits and Systems (Boston, Massachusetts: Kluwer Academic Publishers).
2. Bisdounis, L., Koufopavlou, O., and Nikolaidis, S., 1996, Accurate evaluation of CMOS short-circuit power dissipation for short-channel devices. Proceedings of IEEE International Symposium on Low Power Electronics and Design, pp. 189-192.
3. Burch, R., Najm, F., Yang, P., and TRick, T, 1993, A Monte Carlo approach for power estimation. IEEE Transactions on VLSI Systems, 1, 63-71.
4. Chandrakasan, A., and Brodersen, R., 1995, Low Power Digital Design (Boston, Massachusetts: Kluwer Academic Publishers).
5. Chu, k., and Pulfrey, D., 1986, Design procedures for differential cascode voltage switch circuits. IEEE Journal of Solid-State Circuits, 21, 1082-1087.
6. Devadas, S., Keutzer, k., and White, J., 1992, Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 11, 373-383.
7. Heller, L., Griffin, W, Davis, J., and Thoma, n., 1984, Cascode voltage switch logic: a differential CMOS logic family. Proceedings of IEEE International Solid-State Circuit Conference, pp. 16-17.
8. Kang, S., 1986, Accurate simulation of power dissipation in VLSI circuits. IEEE Journal of Solid-State Circuits, 21, 889-891.
9. Krambeck, R., Lee, c., and Law, H., 1982, High-speed compact circuits with CMOS. IEEE Journal of Solid-State Circuits, 17, 614-619.
10. Lu, S., 1988, Implementation of iterative networks with CMOS differential logic. IEEE Journal of Solid-State Circuits, 23, 1013-1017.
11. Meta-Software, 1966, HSPICE User’s Manual-Version 96.1 (Cambell, California: Meta-Software).
12. Miller, I., Freund, J., and Johnson, R., 1990, Probability and Statistics for Engineers (Englewood Cliffs, New Jersey: Prentice Hall).
13. Mips Technologies, 1994, R4200 Microprocessor Product Information (Mountain View, California: MIPS Technologies Inc).
14. Najm, F., 1994, A survey of power estimation techniques in VLSI circuits. IEEE Transactions on VLSI Systems, 2, 446-455.
15. Oklobdzija, V., and Montope, R., 1986, Design-performance trade-offs in CMOS-domino logic. IEEE Journal of Solid-State Circuits, 21, 304-309.
16. Pfennings, L., Mol, W., Bastiaens, J., and VAn Dirk, J., 1985, Differential split-level CMOS logic for subnanosecond speeds. IEEE Journal of Solid-State Circuits, 20, 1050-1055.
17. Sakurai, T, and Newton, A., 1990, Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas. IEEE Journal of Solid-State Circuits, 25, 585- 594.
18. Schneider, P., Schlichtmann, U., and Wurth, b., 1966, Fast power estimation of large circuits. IEEE Design and Test of Computers Magazine, 13, 70-78.
19. Sun, S., andTsui, P., 1995, Limitation of CMOS supply-voltage scaling by MOSFET threshold voltage. IEEE Journal of Solid-State Circuits, 30, 947-949.
20. Suzuki, M., Ohkubo, N., Shinbo, T, Yamanaka, T, Shimizu, A., Sasaki, K., and Nakagome, Y., 1993, A 1.5-ns 32-b CMOS ALU in double pass-transistor logic. IEEE Journal of Solid-State Circuits, 28, 1145-1151.
21. Xakellis, M., and Najm, F., 1994, Statistical estimation of the switching activity in digital circuits. Proceedings of ACM/IEEE Design Automation Conference, pp. 728-733.
22. Yacoub, G., and Ku, W., 1989, An enhanced technique for simulating short-circuit power dissipation. IEEE Journal of Solid-State Circuits, 24, 844-847.
23. Yano, K., Sasaki, Y., Rikino, K., and Seki, K., 1996, Top-down pass-transistor logic design. iEeE Journal of Solid-State Circuits, 31, 792-803.
24. Yano, K., Yamanaka, T, Nishida, T, Saito, M., Shimohigasi, K., and Shimizu, A., 1990, A 3.8-ns CMOS 16 x 16-b multiplier using complementary pass-transistor logic. IEEE Journal of Solid-State Circuits, 25, 388-395.