A multiple-crystal interface PLL with VCO realignment to reduce phase noise

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 78-79+446+67

  Ye, Sheng ^a   Jansson, Lars ^a   Galton, Ian ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; BANDWIDTH; CMOS INTEGRATED CIRCUITS; INTERFACES (COMPUTER); TRANSCEIVERS; VARIABLE FREQUENCY OSCILLATORS;

POWER SPECTRAL DENSITY (PSD);

PHASE LOCKED LOOPS;

EID: 0036117606     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. A 900 MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications
2. Charge-pump phase-lock loops