A binocular CMOS range image sensor with Bit-serial block-parallel interface using cyclic pipelined ADC's

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 270-271

  Kato, Taichiro ^a   Kawahito, Shoji ^b   Kobayashi, Koji ^a   Sasaki, Hiroshi ^a   Eki, Tatsuya ^a   Hisanaga, Tetsuo ^a  

^a YAMATAKE CORPORATION   (Japan)

^b SHIZUOKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; FAST FOURIER TRANSFORMS; IMAGE QUALITY; IMAGING SYSTEMS; LSI CIRCUITS; OPTICAL SYSTEMS; PIPELINE PROCESSING SYSTEMS;

BINOCULAR CMOS RANGE IMAGE SENSOR; BIT-SERIAL BLOCK-PARALLEL INTERFACE; CYCLIC PIPELINED ANALOG TO DIGITAL CONVERTER; STEREOSCOPIC RANGE IMAGING;

IMAGE SENSORS;

EID: 0242695764     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. V. Brajovic, et al., "100frames/s CMOS Range Image Sensor", ISSCC Digest of Technical Papers, pp. 256-257, Feb., 2001.
2. M. Morikawa, et al., "An Image Processor Implementing Algorithms using Characteristics of Phase Spectrum of Two-Dimensional Fourier Transformation", Proceedings of The IEEE ISIE, vol.3, pp. 1208-1213, Sep., 1999.
3. S. Kawahito, et al., "A Bit-Serial Column Parallel Processing Architecture for On-Sensor Discrete Fourier Transform", Proc. ISCAS, IV, pp. 738-741, May., 2001.
4. S. Kawahito, et al., "A Compressed Digital Output CMOS Image Sensor with Analog 2-D DCT Processors and ADC/Quantizer", ISSCC Digest of Technical Papers, pp. 184-185, Feb., 1997.
5. N. Stevanovic, et al., "A CMOS Image Sensor for High-Speed Imaging", Dig. Tech. Papers, ISSCC, pp. 104-105, Feb., 2000.
6. S. H. Lewis, et al., "A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter", IEEE J. Solid-State Circuits, vol. sc-22, pp.954-961, Dec., 1987.