A bit-serial column parallel processing architecture for on-sensor discrete Fourier transform

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 4, Issue , 2001, Pages 738-741

  Kawahitio, S ^a   Eki, T ^b   Tadokoro, Y ^b  

^a SHIZUOKA UNIVERSITY   (Japan)

^b TOYOHASHI UNIVERSITY OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK FREQUENCY; CMOS IMAGE SENSOR; COLUMN-PARALLEL PROCESSING; COST-EFFECTIVE IMPLEMENTATIONS; HIGH-SPEED PROCESSING; INTEGRATED IMAGES; PROCESSING TIME; REALTIME PROCESSING;

ANALOG TO DIGITAL CONVERSION; DIGITAL CAMERAS;

DISCRETE FOURIER TRANSFORMS;

EID: 0242507799     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.922343     Document Type: Conference Paper

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