Analog and Digital FPGA Implementation of BRIN for Optimization Problems

IEEE Transactions on Neural Networks

Volumn 14, Issue 5, 2003, Pages 1413-1425

  Ng, H S ^a   Lam, K P ^a  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

Analog circuit; Connectionist network; Field programmable gate array (FPGA); Optimization problems; Xilinx XC4010XL

Indexed keywords

GRAPH THEORY; INFERENCE ENGINES; MICROPROCESSOR CHIPS; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; PROBLEM SOLVING; SYSTEMS ANALYSIS;

BINARY RELATION INFERENCE NETWORK (BRIN); BUILDING BLOCK CIRCUIT;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0242695710     PISSN: 10459227     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNN.2003.816375     Document Type: Article

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