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Volumn , Issue , 2003, Pages 693-696

Switching noise reduction techniques for switched-capacitor voltage doubler

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ELECTROMAGNETIC WAVE INTERFERENCE; FREQUENCIES; TRANSISTORS; VOLTAGE REGULATORS;

EID: 0242611688     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (5)

References (6)
  • 1
    • 0016961262 scopus 로고
    • On-chip high-voltage generation in NMOS integrated circuits using an improved voltage multiplier technique
    • June
    • J. F. Dickson, "On-Chip High-Voltage Generation in NMOS Integrated Circuits Using an Improved Voltage Multiplier Technique," IEEE Journal of Solid-State Circuits, vol. SC-11, pp. 374-378, June 1976.
    • (1976) IEEE Journal of Solid-State Circuits , vol.SC-11 , pp. 374-378
    • Dickson, J.F.1
  • 2
    • 0026138627 scopus 로고
    • An experimental 1.5 V 64 Mb DRAM
    • Apr.
    • Y. Nakagome et al., "An Experimental 1.5 V 64 Mb DRAM," IEEE Journal of Solid-State Circuits, vol. 26, pp. 465-472, Apr. 1991.
    • (1991) IEEE Journal of Solid-State Circuits , vol.26 , pp. 465-472
    • Nakagome, Y.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.