A first digitally-controlled oscillator in a deep-submicron CMOS process for multi-GHz wireless applications

IEEE Radio Frequency Integrated Circuits Symposium, RFIC, Digest of Technical Papers

Volumn , Issue , 2003, Pages 81-84

  Staszewski, Robert B ^a   Leipold, Dirk ^a   Hung, Chih Ming ^a   Balsara, Poras T ^b  

^a TEXAS INSTRUMENTS   (United States)

^b Department of Electrical and Computer Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FREQUENCY SYNTHESIZERS; SPURIOUS SIGNAL NOISE; VOLTAGE CONTROL; WIRELESS TELECOMMUNICATION SYSTEMS;

WIRELESS APPLICATIONS;

OSCILLATORS (ELECTRONIC);

EID: 0041589316     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

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2. W. B. Wilson, U. K. Moon, K. R. Lakshmikumar, et al., "A CMOS self-calibrating frequency synthesizer," IEEE Journal of Solid-State Circuits, vol. 35, no. 10, pp. 1437-1444, Oct. 2000.
3. B. Miller, R. J. Conley, "A multiple modulator fractional divider," IEEE Trans. on Instrumentation and Measurement, vol. 40, no. 3, pp. 578-583, June 1991.
4. J. Craninckx, M. Steyaert, Wireless CMOS Frequency Synthesizer Design, Boston, MA: Kluwer Academic, 1998.
5. Y. Matsua et al., "A 16-bit oversampling A/D conversion technology using triple integration noise shaping," IEEE Journal of Solid-State Circuits, vol. SC-22, pp. 921-929, Dec. 1987.